Compared to traditional external dynamic random access memory (DRAM), the embedded DRAM (eDRAM) can work for larger band width with lower power consumption and less chip pins. In the 65 nm generation technology, the frequency performance of the embedded DRAM already exceeds 500 MHz. However, like traditional DRAM, in order to retain the data saved in embedded DRAM, periodical refreshing must be performed to each of the memory elements. The delay of the refreshing structure might limit further development of the system performance of embedded DRAM.
The concurrent refresh (CCR) mode of embedded DRAM allows concurrent implementation of refresh operation and read/write operation. However, in the CCR refresh operation, the target memory bank of the embedded DRAM must be different from the memory bank under current read/write operation, i.e., refresh operation and read/write operation can not be performed to the same memory bank at the same time. There are a plurality of refresh modes for the CCR refresh of embedded DRAM. Single-CCR refers to refreshing only one bank in a refresh cycle, and dual-CCR means refreshing two banks in a refresh cycle. Similarly, quad-CCR means refreshing four banks in each cycle. Moreover, each refresh operation of embedded DRAM can be performed in multiple clock cycles in order to support higher work frequency. Besides the one-stage pipeline operation in which each operation is performed in one clock cycle, the embedded DRAM can also support multiple-stage pipeline operation modes. For two-stage pipeline operation, each of the refresh, read and write operations is completed in two clock cycles; for four-stage pipeline operation, each operation is completed in four clock cycles.
In order to support CCR refresh in various modes, various refresh methods have been provided in the prior art. For example, U.S. Pat. No. 6,195,303 provides a refresh mechanism for DRAM based on clock. However, said mechanism can not be applied to embedded DRAM. A scheduler circuit for avoiding memory confliction in concurrent requests has been provided in U.S. Pat. No. 6,393,534. However, the scheduler circuit can only be applied in RDRAM, not embedded DRAM. And it is too complicated for implementation and synthesis. U.S. Pat. No. 6,967,885 provides an embedded DRAM supporting concurrent refresh mode with distributed row address counters In the 65 nm generation technology, said refresh mode can achieve 1 GHz frequency. The technique of said patent is implemented by adding row address counters inside the embedded DRAM and is a modification to embedded DRAM itself. On the basis of this patent, the present invention controls CCR refresh by adding a refresh controller outside the embedded DRAM.